TSMC CoWoS (Chip-on-Wafer-on-Substrate) capacity must expand to 125,000 wafers/month by 2026 to meet baseline demand from NVIDIA, AMD, and hyperscaler ASICs.
Predictor: Morgan Stanley
Prediction text
TSMC CoWoS (Chip-on-Wafer-on-Substrate) capacity must expand to 125,000 wafers/month by 2026 to meet baseline demand from NVIDIA, AMD, and hyperscaler ASICs. | TSMC CoWoS monthly capacity disclosures
Key catalyst: TSMC CoWoS monthly capacity disclosures
Watch events: TSMC CoWoS monthly capacity; advanced-packaging equipment shipments.
Resolution evidence
TSMC CoWoS capacity ~70k WPM end-2025; on-track expansion toward 120-130k WPM end-2026 per TSMC capex guidance.
Predictor: Morgan Stanley
Calibration plot (stated vs observed)
Evidence about this node from Morgan Stanley is multiplied by κ in /api/intake. Lower κ = less weight; floors at 0.10 (effectively silenced) and caps at 1.00 (full weight).
Reference class: fab_construction_3y
Greenfield semiconductor fab construction within 3 years of announce
Tetlock-style outside view: at TRF=1 (just predicted), outside view dominates (w_in=0.3). At TRF=0 (deadline), inside view dominates (w_in=1.0). The blend regularizes overconfident inside views toward the historical base rate.
Probability over time
Milestone chain
- 2025-12-10hitNVIDIA secures ≥50% of TSMC CoWoS capacity for 2026-27How: DigiTimes / Wedbush / Astute Group reporting confirms NVIDIA holds 50%+ of TSMC's projected CoWoS capacity for 2026-27Source: DigiTimes — TSMC expands CoWoS capacity with Nvidia booking over half for 2026-27conf 97%
- 2026-01-01hitTSMC pivots toward CoWoS-L using Local Silicon Interconnect bridge architectureHow: TSMC publicly confirms CoWoS-L (LSI Bridge) as core packaging technology to enable larger AI chips beyond reticle limitSource: TokenRing/FinancialContent — The Great Packaging Pivot (Jan 2026)conf 95%
- 2026-01-20hitAMD allocated ~11% of CoWoS capacity for MI350/MI400 rampHow: AMD's CoWoS allocation publicly disclosed at ~11% (vs NVIDIA 50%+, Broadcom remainder)Source: Wedbush — The Great AI Packaging Squeezeconf 85%
- 2026-03-07overdueQ1 window check-in (25%)
- 2026-04-08hitTSMC US-Arizona advanced packaging capacity expansion announcedHow: TSMC announces US-based advanced packaging line expansion specifically for AI customersSource: CNBC — Nvidia snaps up AI chip packaging capacity as TSMC expands in U.S.conf 85%
- 2026-05-11overdueQ2 window check-in (50%)
- 2026-07-15pendingQ3 window check-in (75%)
- 2026-10-01 → 2026-12-31pendingTSMC monthly CoWoS capacity reaches 127,000-130,000 wafers by end-2026How: TSMC monthly disclosures or DigiTimes/Tiger Brokers reporting confirm CoWoS monthly capacity ≥125,000 wafers by year-end 2026Source: FinancialContent — TSMC to Quadruple Advanced Packaging Capacity to 130,000 CoWoS Wafers Monthly by Late 2026 (Feb 2026)conf 90%Notes: Direct measurement of 125K wafers/month claim. Reuters/DigiTimes specifically cite 127,000 figure.
- 2026-06-01 → 2027-12-31pendingCoWoS capacity remains binding constraint causing AI accelerator shortages through 2027How: Industry analyst reports continue to cite CoWoS as primary AI accelerator capacity constraint through 2027Source: FusionWW — Inside the AI Bottleneck: CoWoS, HBM, and 2-3nm Capacity Constraints Through 2027conf 70%
What if this resolves?
Click a button to clamp this prediction and run a Gibbs sample. Returns the predictions whose marginals shift most. ~30s per run; ideal for stress-testing "if X resolves, what else moves?"
Evidence chain
Raw metadata
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}Raw metadata
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}Raw metadata
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}Network propagation neighbors
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Ticker exposure
Beneficiaries (24)
Prerequisites (2)
Dependents (0)
| Type | Pred | Title | Domain | Lag |
|---|---|---|---|---|
| No dependents | ||||
Linked documents (2)
| Sim | Source | Title | Market prob | Polarity | Reviewed | Published |
|---|---|---|---|---|---|---|
| 0.647 | manifold | When will Codex hit 6M WAUs? | — | mentions | pending | 2026-06-01 |
| 0.578 | edgar_8k | MOSAIC CO (MOS) (CIK 0001285785) | — | mentions | pending | 2026-05-29 |
Raw metadata
{
"nia": false,
"qty": "125k wafers/mo",
"mode": "FORECAST",
"role": "Cited-Firm",
"context": "Advanced packaging is the second binding constraint behind HBM; CoWoS is the architectural glue for AI silicon.",
"to_year": 2026,
"cited_by": "Synthesis report",
"conv_cues": "specific capacity; MS research",
"direction": "NUMERIC_TARGET",
"from_year": 2026,
"timeframe": "by 2026",
"conv_level": "HIGH",
"milestones": [
{
"kind": "llm_pre_event",
"label": "NVIDIA secures ≥50% of TSMC CoWoS capacity for 2026-27",
"source": "DigiTimes — TSMC expands CoWoS capacity with Nvidia booking over half for 2026-27",
"status": "hit",
"weight": 0.4,
"ordinal": -7,
"source_id": null,
"confidence": 0.97,
"source_url": "https://www.digitimes.com/news/a20251210PD218/tsmc-cowos-capacity-nvidia-equipment.html",
"expected_date": "2025-12-10",
"observed_date": "2025-12-10",
"research_origin": "deep_research",
"measurement_criterion": "DigiTimes / Wedbush / Astute Group reporting confirms NVIDIA holds 50%+ of TSMC's projected CoWoS capacity for 2026-27"
},
{
"kind": "llm_pre_event",
"label": "TSMC pivots toward CoWoS-L using Local Silicon Interconnect bridge architecture",
"source": "TokenRing/FinancialContent — The Great Packaging Pivot (Jan 2026)",
"status": "hit",
"weight": 0.4,
"ordinal": -6,
"source_id": null,
"confidence": 0.95,
"source_url": "https://markets.financialcontent.com/wral/article/tokenring-2026-1-1-the-great-packaging-pivot-how-tsmc-is-doubling-cowos-capacity-to-break-the-ai-supply-bottleneck-through-2026",
"expected_date": "2026-01-01",
"observed_date": "2026-01-01",
"research_origin": "deep_research",
"measurement_criterion": "TSMC publicly confirms CoWoS-L (LSI Bridge) as core packaging technology to enable larger AI chips beyond reticle limit"
},
{
"kind": "llm_pre_event",
"label": "AMD allocated ~11% of CoWoS capacity for MI350/MI400 ramp",
"source": "Wedbush — The Great AI Packaging Squeeze",
"status": "hit",
"weight": 0.4,
"ordinal": -5,
"source_id": null,
"confidence": 0.85,
"source_url": "https://investor.wedbush.com/wedbush/article/tokenring-2026-1-20-the-great-ai-packaging-squeeze-nvidia-secures-50-of-tsmc-capacity-as-sk-hynix-breaks-ground-on-p-and-t7",
"expected_date": "2026-01-20",
"observed_date": "2026-01-20",
"research_origin": "deep_research",
"measurement_criterion": "AMD's CoWoS allocation publicly disclosed at ~11% (vs NVIDIA 50%+, Broadcom remainder)"
},
{
"kind": "quartile_checkpoint",
"label": "Q1 window check-in (25%)",
"status": "overdue",
"weight": 0.05,
"ordinal": -4,
"source_id": null,
"expected_date": "2026-03-07",
"observed_date": null,
"miss_emitted_at": "2026-05-02T22:07:21.384228+00:00",
"miss_emitted_by": "metadata_milestone_sweep"
},
{
"kind": "llm_pre_event",
"label": "TSMC US-Arizona advanced packaging capacity expansion announced",
"source": "CNBC — Nvidia snaps up AI chip packaging capacity as TSMC expands in U.S.",
"status": "hit",
"weight": 0.4,
"ordinal": -3,
"source_id": null,
"confidence": 0.85,
"source_url": "https://www.cnbc.com/2026/04/08/tsmc-nvidia-advanced-packaging-intel.html",
"expected_date": "2026-04-08",
"observed_date": "2026-04-08",
"research_origin": "deep_research",
"measurement_criterion": "TSMC announces US-based advanced packaging line expansion specifically for AI customers"
},
{
"kind": "quartile_checkpoint",
"label": "Q2 window check-in (50%)",
"status": "overdue",
"weight": 0.05,
"ordinal": -2,
"source_id": null,
"expected_date": "2026-05-11",
"observed_date": null,
"miss_emitted_at":
... (truncated)